1. Technical Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly to electrically programmable three-dimensional (3-D) memory.
2. Related Arts
In a three-dimensional (3-D) integrated circuit (3D-IC), one or more 3D-IC layers are stacked one above another on top of a substrate. Each IC layer comprises functional blocks such as logic, memory and analog blocks. It is typically comprised of non-single-crystalline (poly, microcrystalline or amorphous) semiconductor material. Because logic and analog blocks are sensitive to defects and non-single-crystalline semiconductor material has a large defect density, the 3D-IC comprising logic and/or analog blocks have a low yield. Moreover, logic and/or analog blocks consume large power. The three-dimension integration of these blocks faces many heat-dissipation issues. On the other hand, a memory block is less sensitive to defects because the defect-induced errors can be corrected (by, for example, redundancy circuit). Moreover, it consumes little power. Accordingly, memory is better suited for the 3-D integration.
In a three-dimensional memory (3D-M), one or more memory levels are stacked one above another on top of a substrate. As illustrated in FIG. 1, the two physical memory levels 100, 200 of the 3D-M 0 are stacked one by one on a substrate 0s. On each memory level 100, there are a plurality of address-select lines (including word line 20a and bit line 30a) and 3D-M cells (1aa . . . ). Substrate 0s comprises a plurality of transistors. Contact vias (20av, 30av . . . ) provide electrical connection between address-select lines (20a, 30a . . . ) and the substrate circuit.
The 3D-M can be categorized through the means employed to alter its contents. If the contents can be altered using electrical means, this 3D-M is an electrically programmable 3D-M (EP-3DM); if the contents are altered using non-electrical means, then this 3D-M is a non-electrically programmable 3D-M (NEP-3DM).
The electrically programmable 3D-M (EP-3DM) can be further categorized into 3-D RAM (3D-RAM), 3-D write-once memory (a.k.a. 3-D one-time programmable, i.e. 3D-OTP), and 3-D write-many (3D-WM). The 3D-RAM cell is similar to a conventional RAM cell except that the transistors used therein are thin-film transistors (TFT) 1t (FIG. 1B). The 3D-OTP cell may comprise a 3D-ROM layer 22 (e.g. a diode layer. The details of the 3D-ROM layer are referred to U.S. Pat. No. 5,835,396) and an antifuse layer 22a (FIG. 1C). The integrity of the antifuse layer 22a indicates the logic state of the 3D-OTP cell. The 3D-WM includes 3D-flash, 3D-MRAM (3-D magneto-resistive-material-based RAM), 3D-FRAM (3-D Ferroelectric-material-based RAM), 3D-OUM (3-D Ovonyx-unified-memory), etc. It may comprise active devices such as TFT 1t (FIGS. 1DA-1DB). The TFT-based 3D-WM may comprise a floating gate 30fg (FIG. 1DA) or a vertical channel 25c (FIG. 1DB).
An exemplary non-electrically programmable 3D-M (NEP-3DM) is mask-programmable 3-D read-only memory (3D-MPROM). It represents logic “1” with the existence of an info-via 24 (i.e. absence of dielectric 26) (FIG. 1EA); and logic “0” with the absence of an info-via (i.e. existence of dielectric 26) (FIG. 1EB). Similar to 3D-OTP cell (FIG. 1C), it also comprises a 3D-ROM layer 22 (e.g. a diode layer).
3D-M can also be categorized as conventional semiconductor memory, i.e. it can be categorized into 3D-RAM and 3D-ROM (including 3D-MPROM, 3D-OTP, 3D-WM). This is the approach used by prior patents and patent applications filed by the same inventor (U.S. Pat. No. 5,835,396, U.S. patent application Ser. No. 10/230,648, etc.) In this application, both categorizations are used interchangeably.
With low-cost, high density and large bandwidth, the 3D-M has a strong competitive edge. However, because it is typically based on non-single-crystalline semiconductor, the performance of the 3D-M cell cannot yet compete with the conventional memory. For the 3D-M designed and manufactured in conventional approaches, its performance, such as read-write speed, unit-array capacity, intrinsic yield and programmability, needs further improvement.
The present invention provides an improved three-dimensional memory (3D-M). It has better integratibility, speed, density/cost and programmability. The 3D-M can be used to form three-dimensional integrated memory (3DiM), e.g. computer-on-a-chip (ConC) and player-on-a-chip (PonC). ConC/PonC offers excellent data security. Another 3D-M application of great importance is in the area of the integrated-circuit (IC) testing. 3D-M carrying the IC test data can be integrated with the circuit-under-test (CUT), thus enabling at-speed test and self-test.
It should be noted that, although various types of the 3D-M (including both EP-3DM and NEP-3DM) are described hereinafter, the scope of this Application is limited to the EP-3DM only. The NEP-3DM is expressly excluded from the scope of this Application.